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| W83194BR-C 200MHZ CLOCK FOR CAMINO CHIPSET 1.0 GENERAL DESCRIPTION The W83194BR-C is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-C provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 different frequencies of CPU, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR-C provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.75% center type spread spectrum to reduce EMI. The W83194BR-C accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES * * * * * * * * * * * * * * * * 2 CPU clock outputs One CPU/2 output as reference input to DRCG 3 3V66 clock outputs 3 IOAPIC clock outputs 8 PCI synchronous clocks. Optional single or mixed supply: (VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V) CPU to 3V66 offset .0 to 1.5 ns 3V66 to PCI offset 1.5 to 4.0 ns Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz I2C 2-Wire serial interface and I2C read back 0.5% and 0.75% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz pins for USB 24 MHz for super I/O 48-pin SSOP package -1- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 3.0 PIN CONFIGURATION IOAPIC 2 REF2X VDDQ3 Xin Xout VSS PCICLK0/ *FS2 PCICLK1/ *FS1 VDDQ3 PCICLK2 PCICLK3 PCICLK4 PCICLK5 VSS PCICLK6 PCICLK7/FS3# VDDQ3 PCICLK8 PCICLK9 VSS 3V66-0 3V66-1 3V66-2 VDDQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VddQ2 IOAPIC0 IOAPIC 1 VSS VDDQ2 CPU/2 VSS VDDQ2 CPUCLK2 VSS VDDQ2 CPUCLK1 CPUCLK0 *SDATA VDDQ3 VSS PD# *SDCLK VDDQ3 *24_48MHz /SIO 48MHz/ *FS0 VSS SEL133/100# -2- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 4.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull-up 4.1 Crystal I/O SYMBOL Xin Xout PIN 4 5 I/O IN OUT FUNCTION Crystal input with internal loading capacitors and feedback resistors. Crystal output at 14.318MHz nominally. 4.2 CPU, 3V66, PCI, IOAPIC Clock Outputs SYMBOL CPUCLK [0:2] CPU/2 PD# SEL133/100# PCICLK0/ *FS2 PIN 45,44 42 31 25 7 I/O OUT O IN IN I/O FUNCTION Low skew (< 250ps) clock outputs for host frequencies such as CPU and Chipset. As a reference signal for DRCG. The voltage is determined by VDDQ2. Power Down mode when driven low. Frequency selection input pin. 3.3V PCI clock during normal operation. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. Low skew (< 250ps) PCI clock outputs. Low skew (< 250ps) PCI clock outputs. Latched input for FS3 at initial power up for H/W selecting the output frequency of CPU, SDRAM and PCI clocks. 3.3V output clocks for the chipset. Synchronous with CPU clocks, 2.5V. PCICLK1/ *FS1 8 I/O PCICLK[2,8:9] PCICLK7/ *FS3 10,11,12,13,15 ,18,19 16 I/O I/O 3V66 [0:2] IOAPIC[0:2] 21, 22, 23 46, 45, 1 OUT O -3- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 4.3 I2C Control Interface SYMBOL *SDATA *SDCLK PIN 34 30 I/O I/O IN 2 FUNCTION Serial data of I C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor. 4.4 Fixed Frequency Outputs SYMBOL IOAPIC[0:2] REFX2 24_48MHz/ *SIO PIN 46, 45, 1 2 28 I/O O I/O I/O FUNCTION Synchronous with CPU clocks, 2.5V. 14.318MHz reference clock. 24MHz or 48MHz output clock. Latched input for SIO at initial power up for the output frequency of 24MHz(HIGH) and 48MHz(LOW) clocks. 48MHz/ FS0* 27 I/O 48MHz / Latched input for FS0 at initial power up for H/W selecting the output frequency. 4.5 Power Pins SYMBOL VddQ2 VddQ3 Vss PIN 37,40,43,47 3,9,17,24,29,33 FUNCTION Power supply for CPU & IOAPIC, 2.5V Power supply for PCI,3V66,REF2X,48MHz output,3.3V. 6,14,20,26,32,38,41, Circuit Ground. 44,48 -4- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 5.0 Frequency Selection by Hardware FS4 FS3 FS2 FS1 FS0 CPU(MHz) 133.90 128.50 124.00 66.80 120.00 114.00 105.00 100.20 160.00 155.00 152.50 150.00 148.00 143.00 138.00 133.30 100.90 109.00 116.00 122.00 126.00 130.00 135.00 140.00 145.00 159.00 162.00 165.00 168.00 171.00 174.00 180.00 CPU/2 66.95 64.25 62.00 33.40 60.00 57.00 52.50 50.10 80.00 77.50 76.25 75.00 74.00 71.50 69.00 66.65 50.45 54.50 58.00 61.00 63.00 65.00 67.50 70.00 72.50 79.50 81.00 82.50 84.00 85.50 87.00 90.00 3V66/CPU 0.50 0.50 0.67 1.00 0.67 0.67 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 3V66(MHz) 66.95 64.25 82.67 66.80 80.00 76.00 70.00 66.80 80.00 77.50 76.25 75.00 74.00 71.50 69.00 66.65 50.45 72.67 77.34 61.00 63.00 65.00 67.50 70.00 72.50 79.50 81.00 82.50 84.00 85.50 87.00 90.00 PCI(MHz) 33.48 32.13 41.34 33.40 40.00 38.00 35.00 33.40 40.00 38.75 38.13 37.50 37.00 35.75 34.50 33.33 25.23 36.34 38.67 30.50 31.50 32.50 33.75 35.00 36.25 39.75 40.50 41.25 42.00 42.75 43.50 45.00 IOAPIC (MHz) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16.74 16.06 20.67 16.70 20.00 19.00 17.50 16.70 20.00 19.38 19.06 18.75 18.50 17.88 17.25 16.66 12.61 18.17 19.33 15.25 15.75 16.25 16.88 17.50 18.13 19.88 20.25 20.63 21.00 21.38 21.75 22.50 -5- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.0 SERIAL CONTROL REGISTERS The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. Frequency Selection BY I2C SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHz) 133.90 128.50 124.00 66.80 120.00 114.00 105.00 100.20 160.00 155.00 152.50 150.00 148.00 143.00 138.00 133.30 100.90 109.00 116.00 122.00 126.00 130.00 135.00 140.00 145.00 159.00 162.00 165.00 168.00 171.00 174.00 180.00 CPU/2 66.95 64.25 62.00 33.40 60.00 57.00 52.50 50.10 80.00 77.50 76.25 75.00 74.00 71.50 69.00 66.65 50.45 54.50 58.00 61.00 63.00 65.00 67.50 70.00 72.50 79.50 81.00 82.50 84.00 85.50 87.00 90.00 3V66 (MHz) 66.95 64.25 82.67 66.80 80.00 76.00 70.00 66.80 80.00 77.50 76.25 75.00 74.00 71.50 69.00 66.65 50.45 72.67 77.34 61.00 63.00 65.00 67.50 70.00 72.50 79.50 81.00 82.50 84.00 85.50 87.00 90.00 PCI (MHz) 33.48 32.13 41.34 33.40 40.00 38.00 35.00 33.40 40.00 38.75 38.13 37.50 37.00 35.75 34.50 33.33 25.23 36.34 38.67 30.50 31.50 32.50 33.75 35.00 36.25 39.75 40.50 41.25 42.00 42.75 43.50 45.00 IOAPIC (MHz) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16.74 16.06 20.67 16.70 20.00 19.00 17.50 16.70 20.00 19.38 19.06 18.75 18.50 17.88 17.25 16.66 12.61 18.17 19.33 15.25 15.75 16.25 16.88 17.50 18.13 19.88 20.25 20.63 21.00 21.38 21.75 22.50 -6- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU (MHz) 134.00 135.00 136.00 137.00 139.00 141.00 142.00 144.00 146.00 147.00 149.00 151.00 152.00 153.00 154.00 157.00 158.00 161.00 163.00 164.00 166.00 167.00 169.00 170.00 172.00 173.00 175.00 181.00 183.00 185.00 190.00 200.00 CPU/2 67.00 67.50 68.00 68.50 69.50 70.50 71.00 72.00 73.00 73.50 74.50 75.50 76.00 76.50 77.00 78.50 79.00 80.50 81.50 82.00 83.00 83.50 84.50 85.00 86.00 86.50 87.50 90.50 91.50 92.50 95.00 100.00 3V66 (MHz) 67.00 67.50 68.00 68.50 69.50 70.50 71.00 72.00 73.00 73.50 74.50 75.50 76.00 76.50 77.00 78.50 79.00 80.50 81.50 82.00 83.00 83.50 84.50 85.00 86.00 86.50 87.50 90.50 91.50 92.50 95.00 100.00 PCI (MHz) 33.50 33.75 34.00 34.25 34.75 35.25 35.50 36.00 36.50 36.75 37.25 37.75 38.00 38.25 38.50 39.25 39.50 40.25 40.75 41.00 41.50 41.75 42.25 42.50 43.00 43.25 43.75 45.25 45.75 46.25 47.50 50.00 IOAPIC (MHz) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16.75 16.88 17.00 17.13 17.38 17.63 17.75 18.00 18.25 18.38 18.63 18.88 19.00 19.13 19.25 19.63 19.75 20.13 20.38 20.50 20.75 20.88 21.13 21.25 21.50 21.63 21.88 22.63 22.88 23.13 23.75 25.00 -7- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.1 Register 0: CPU Frequency Select Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description SSEL3 ( Frequency table selection by software via I2C) SSEL2 ( Frequency table selection by software via I2C) SSEL1 ( Frequency table selection by software via I2C) SSEL0 ( Frequency table selection by software via I2C) 0 = Selection by hardware 1 = Selection by software I2C - Bit (1,2, 6:4) SSEL4 (Frequency table selection by software via I2C ) SSEL5 (Frequency table selection by software via I2C ) 0 = Normal 1 = Spread Spectrum enabled 6.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 0 1 0 1 1 1 Pin 27 28 42 39 36 35 Description 48MHz(Active / Inactive) 24_48MHz(Active / Inactive) 0 = 0.25% Center type Spread Spectrum Modulation 1 =0.5% Center type Spread Spectrum Modulation CPU/2(Active / Inactive) 0 = Running 1 = Tristate all outputs CPUCLK2(Active / Inactive) CPUCLK1(Active / Inactive) CPUCLK0(Active / Inactive) 6.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 16 15 13 12 11 10 8 7 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK0 (Active / Inactive) Description -8- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.4 Register 3: 3V66 Clock Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 1 0 0 1 1 Pin 23 22 21 19 18 Reserve 3V66_2(Active / Inactive) 3V66_1(Active / Inactive) 3V66_0(Active / Inactive) Reserve Reserve PCICLK9 (Active / Inactive) PCICLK8 (Active / Inactive) Description 6.5 Register 4: PCI Clock Additional Register (1 = Active, 0 = Inactive) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 1 1 1 0 0 0 1 Pin 1 45 46 2 Description 0 = Center type Spread Spectrum Modulation 1 =0~0.5% Down type Spread Spectrum (Override register bit5) IOAPIC2 (Active / Inactive) IOAPIC1 (Active / Inactive) IOAPIC0 (Active / Inactive) Reserve Reserve Reserve REF2X (Active / Inactive) 6.6 Register 5: Skew Register Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 X X X X X Pin Description Skew2 (CPU to 3V66 skew program bit) Skew1 (CPU to 3V66 skew program bit) Skew0 (CPU to 3V66 skew program bit) FS3# SEL133/100# FS2# FS1# FS0# -9- Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.7 Register 6: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description 5.8 Register 7: Winbond Chip ID Register (Read Only) Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 1 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID Description 6.9 Register 8: Watchdog Timer Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Enable Count Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0 - 10 - Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.10 Register 9: M/N Program Register and 3V66 Divisor Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 8 3V66 divisor 3V66 divisor M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 00: CPU/2 ; 01: CPU/1.5 10: CPU/1 ; 11: CPU/3 Description 6.11 Register 10: M/N Program Register Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 Description 6.12 Register 11: Divisor Register Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin Description Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3] - 11 - Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 6.12 Register 12 Divisor Register Bit 7 @PowerUp 0 Pin 0: use frequency table 1: use M/N register 9~12 to program frequency Freq. = 14.318MHz * (N+4)/ 2*M 6 5 4 3 2 1 0 1 1 1 1 1 1 1 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Description 7.0 ORDERING INFORMATION Part Number W83194BR-C Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C 8.0 HOW TO READ THE TOP MARKING W83194BR-C 28051234 814GBB 1st line: Winbond logo and the type number: W83194BR-C 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR B: Winbond internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 12 - Publication Release Date: Dec. 1999 Revision 0.40 W83194BR-C PRELIMINARY 9.0 PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 Winbond Electronics (North America) Corp. 2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 13 - Publication Release Date: Dec. 1999 Revision 0.40 |
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